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alu
- 一个简单的算术逻辑运算模块的Verilog代码，可进行加、减、自增、自减，比较大小等运算-alu module
final-project
- Verilog 的Branch和Jump指令的实现 添加了MUX和额外的ALU-Verilog Branch and Jump instructions achieve add the MUX and additional ALU
alu
- It is 32 bit ALU code in Verilog HDL programming Language
ALU
- MIPS ALU written using Verilog HDL. Computer structure project
alu.v
- a well written and yet small verilog hardware descr iption language or popularly known as simply Verilog program for an Arithmetic and Logic Unit or as popularly called ALU
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
ALU
- verilog编写，八位ALU，加减与或比较-verilog prepared eight ALU, subtract, or compare with
alu
- alu,利用verilog实现+、-、*、 、移位等功能-alu achieve+,-,*, , shift functions
alu
- 32位alu模块实现加减法、逻辑运算、移位、比较和置高位立即数等功能。verilog实现。-32-bit alu module achieves functions like addition and subtraction, logical operations, shift, compare, and set a high immediate number by verilog
alu
- verilog 编写的 可综合的ALU单元 可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
ALU-and-Register-File
- ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
ALU
- ALU，两种类型的verilog源代码，包括测试代码，原创。-ALU, two types of verilog source code, including test code, originality.
8-bit-ALU-with-a-Newton-Raphson-Divider
- 8-bit ALU with a Newton-Raphson Divider Using Verilog
ALU
- 自己编写的Verilog ALU 效果还不错 可以-Verilog ALU
alu
- verilog code for 8 bit alu
alu
- My own arithmetic and logic unit in Verilog HDL.
alu
- 用Verilog HDL编写的简单算数逻辑单元-Algorithm Logic Unit programmed by Verilog HDl
alu
- 用Verilog语言中的always块实现对输入数据执行加、减、与、或和求反的功能-Using Verilog language always realize the input data block to perform addition, subtraction, AND, OR, and negated function
ALU
- 用verilog寫成的ALU，有簡易的加減乘除、shifting、logic gate等功能。-Written by verilog ALU, there is a simple addition, subtraction, shifting, logic gate functions.
CPU_Verilog
- 此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)